Project leader of a group of 5 engineers writing the run-time
support software for a hardware VHDL behavioral simulator. This
included design partitioning among multiple processors per board
and multiple boards per simulator, symbol table creation and
manipulation, downloading of the simulation code and the run-time
kernel to the target hardware, text and file i/o support, and
support for debugging (breakpoints, trace, browsing). Responsible
for the Browser subsystem. Work involved coordination with the
compiler and hardware groups at Zycad, as well as with our partner
companies (including Synopsis, Cadence, Dazix, Vantage, and others)
who provide the simulation front end to ViP software. ViP (VHDL
Instruction Processor) was a new product, introduced at DAC 92.
Development environment was Sun Sparcs, Unix, ANSI C (gcc), as
well as Mips for embedded code. Host side software was also to
be ported to RS6000, HP/Apollo, and other engineering workstations.
Designed and implemented a clock tree
analysis program which parsed several ASCII layout and technology
files, calculated time delays and skews for multi-level clock
trees using an RC-tree approximation, reported statistics at all
levels of the tree, and created Spice decks for the four extremal
nets as well as any single net the user might select. Environment
was Sun Sparc, Unix, and C.
Designed and implemented a CAD Framework Initiative (CFI) procedural
interface to the EDI database (which is based on EDIF, the
Electronic Design Interchange Format). Extended the functionality
of the EDI procedural interface
to support this project, including implementing a schematic to net
list translator. Computers used were 386-based PC's under DOS, and
an Apollo DN3000 under AEGIS; language was C.